1. Field of the Invention
The present invention relates to a data processing apparatus and method for connection to interconnect circuitry.
2. Description of the Prior Art
Within a data processing system, it is known to provide one or more resources which are shared amongst a plurality of elements of the data processing system. For example, the plurality of elements may take the form of a plurality of master devices, and the shared resource may take the form of a slave device with respect to which the various master devices can initiate transactions. Each transaction typically consists of an address transfer from a master device to a slave device, and one or more data transfers between the master device and the slave device. For a write transaction, these data transfers will pass from the master device to the slave device (in some implementations there will additionally be a write response transfer from the slave device to the master device), whilst for a read transaction these data transfers will pass from the slave device to the master device.
To enable each transaction to take place, a communication path needs to be established between the master device initiating the transaction, and the slave device to which the transaction is directed. Typically, the mechanism used to establish the communication paths between master devices and slave devices is shared amongst the various master and slave devices. For example, a data processing system may provide interconnect circuitry for coupling the various master devices and slave devices, with the interconnect circuitry providing a plurality of connection paths over which such communication paths can be established.
One type of master device which it is known to connect to an interconnect circuit is a general purpose processor, often referred to as a processor core or a central processing unit (CPU). However, another type of processing device which has been developed to provide a lower cost processing device than the general purpose processor is a processing unit optimised for handling specific processing tasks, such a processing unit being referred to herein as a data engine. Whilst a data engine may have its own dedicated resources, for example its own interrupt controller, its own Direct Memory Access (DMA) logic, etc, in other embodiments the data engine may have no local resources dedicated to it, such a data engine often being arranged to act as a pure slave device for a main processing unit such as the earlier mentioned general purpose processor. Further, as a middle ground approach, some data engines can be arranged to have access to certain resources, but with those resources being shared with other elements of the data processing system. In such embodiments, whilst those resources, or portions of those resources, may be dedicated to the data engine for a particular session (a session typically containing a group of tasks to be performed), those resources can be re-allocated in a subsequent session to other elements of the data processing system.
However the data engine is constructed, the data engine will often have a significantly reduced level of hardware when compared with the general purpose processor, with that hardware being software controlled to perform the desired specific processing tasks allocated to that data engine.
It would be desirable to enable such a data engine to be coupled to interconnect circuitry to operate as a master device with respect to the interconnect circuitry. However, interconnect circuits typically employ interconnect protocols that control the routing of traffic through the interconnect circuitry, and hence if such a data engine were to be connected to an interconnect circuit, it would need to be provided with the necessary structure at its interface to enable it to initiate transactions conforming to the interconnect protocol. Given that the interface will add functionality that is not part of the core data engine function, it would be advantageous for any such interface mechanism enabling the data engine to communicate with the interconnect circuit to have a low hardware requirement.
Further, from a flexibility standpoint, it would be desirable for any such interface mechanism to not be constrained to any particular interconnect protocol, to enable the data engine to be coupled to a variety of different interconnect circuits employing different interconnect protocols.
In the area of microcontroller technology, it is known to use software executing on the microcontroller to drive general purpose input/output pins in order to produce signals conforming to certain bus protocols, typically those associated with serial buses to which the microcontroller may be connected.